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Data Sheet
ADE7880
Bit
18
Mnemonic
REVPSUM3
Default Value
0
Description
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in
the CF3 data path changes sign.
19
HREADY
0
When this bit is set to 1, it enables an interrupt when the harmonic block output
registers have been updated. If Bit 1 (HRCFG) in HCONFIG register is cleared to 0, the
interrupt is triggered every time the harmonic calculations are updated at 8 kHz
rate. If Bit HRCFG is set to 1, the interrupt is triggered every time the harmonic
calculations are updated at 8 kHz rate starting 750 ms after the harmonic block
setup.
31:19
Reserved
00 0000 0000
Reserved. These bits do not manage any functionality.
0000
Table 39. MASK1 Register (Address 0xE50B)
Bit
0
Mnemonic
NLOAD
Default Value
0
Description
When this bit is set to 1, it enables an interrupt when at least one phase enters no
load condition determined by the total active power and VNOM based apparent
power.
1
FNLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no
load condition based on fundamental active and reactive powers.
2
VANLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no
load condition based on apparent power.
3
ZXTOVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A
voltage is missing.
4
ZXTOVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B
voltage is missing.
5
ZXTOVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C
voltage is missing.
6
ZXTOIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A
current is missing.
7
ZXTOIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B
current is missing.
8
ZXTOIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C
current is missing.
9
ZXVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase A voltage.
10
ZXVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase B voltage.
11
ZXVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase C voltage.
12
ZXIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase A current.
13
ZXIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase B current.
14
ZXIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on
Phase C current.
15
RSTDONE
0
Because the RSTDONE interrupt cannot be disabled, this bit does not have any
functionality attached. It can be set to 1 or cleared to 0 without having any effect.
16
SAG
0
When this bit is set to 1, it enables an interrupt when one of the phase voltages
entered or exited a sag state. The phase is indicated by Bits[14:12] (VSPHASE[x]) in
the PHSTATUS register (see Table 40).
17
OI
0
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs
on one of the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register
(see Table 40).
18
OV
0
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs
on one of the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register
(see Table 40).
19
SEQERR
0
When this bit is set to 1, it enables an interrupt when a negative-to-positive zero
crossing on Phase A voltage is not followed by a negative-to-positive zero crossing
on Phase B voltage, but by a negative-to-positive zero crossing on Phase C voltage.
Rev. A| Page 93 of 104
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